Formalising Configuration Relocation Behaviours for Reconfigurable Computing

Although the partially reconfigurable FPGA design is powerful if two different configurations were mapped at compile time to overlapping locations in the FPGA, only one of these configurations can be present in the array at any given moment. They cannot operate simultaneously. However, if somehow the final FPGA location can be determined at runtime, one or both of these overlapping configurations can be relocated to a new location that was previously unused to allow for simultaneous use. The configurations can be relocated by either rotation or shifting in an FPGA fabric. In this paper, our research has shown that the relocating configurations can be specified and reasoned formally by algebraic laws for checking whether a chip of given size and a given feasible schedule allow a feasible placement. Our examination is done on a generic partially reconfigurable FPGA and Ruby algebra is used to specify and reason in this case.